High Data Rate 8-Bit Crypto Processor

This paper describes a high data rate 8-bit Crypto Processor based on Advanced Encryption Standard (Rijndael algorithm). Though the algorithm requires 32-bit wide data path but our novel mix-column architecture makes the algorithm works in a true byte systolic fashion. Initial stages are merged to remove dependency of completion of these stages on mix-column stage. It has resulted in the optimization of data path utilization and bus width thus minimizing control logic, area and power. Most of the commercially available AES crypto processors use different hardware modules to handle Key Expansion and Data Encryption. The paper also presents a novel approach to handle both the key expansion and data encryption phases by re-using the same hardware architecture. The proposed design saves many hardware resources when mapped on FPGA and allows operation at high clock frequencies and data rates.